The present invention relates to a virtual storage address space access control system for carrying out an access control of a virtual storage address space in a multi-virtual storage system and more particularly to a virtual storage address space access control system for performing an address translation from a virtual address to a real address at high speed.
In a conventional multi-virtual storage system, only access to the data in the address space designated by the control register is allowed. In order to refer to data in a plurality of address spaces, it is necessary to swap the content of the control register and the process of swapping the content of the control register is performed under the control of an operating system. It is impossible for a user program to carry out the process of data extending over a plurality of address spaces.
However, the amount of data to be dealt with by the data process system has greatly increased. Thus, a multi-virtual storage system with a new architecture for enabling a user's program to directly access data in an extremely large number of address spaces has been proposed. In such a multi-virtual storage system, a segment table necessary for performing the address translation can be accessed at high speed and a process for translating a virtual address to a real address needs to be realized.
Recently, a multi-virtual storage system with a new architecture using an access register has been put on the market.
As shown in FIG. 1, in the multi-virtual storage system, an access list is pointed to by the content (called ALET (access list entry table), hereinafter) of the access register accessed by a base register number and an ASN second table is pointed to by this access list. The segment table is designated in accordance with the segment table designation (abbreviated to STD in FIG. 1) determined by the ASN second table. Thus, the address translation from the virtual address to the real address can be adapted by using the dynamic address translation structure. In this structure, the user program loads ALET into 16 access registers. Thus, it is possible to access to an access list having a capacity of 1K or 4k. This makes it possible to select an extremely large number of segment table designations. Thus, a multi-virtual storage with a very large capacity can be utilized.
A computer system having a capacity of 2.sup.47 bytes as a logical space appears. In this case, when one page comprises 4K bytes, the number of logical pages is 2.sup.35. Therefore, it becomes very expensive if the page table is provided as a special hardware and the page table makes the effective physical space narrower when it is provided in a main storage. In this case, the logical space comprises one level comprising one page. A dynamic address translation (DAT) divides the logical page into segment number and page number and provides the page table in a normal logic space. Such method is called multi-level paging. In this case, the system comprises two levels comprising the segment table and the page table.
As shown in FIG. 2, the .alpha.-th record's content PTO counting from the head of the predetermined segment table is derived from the segment number .alpha. of the segment table and then the head address of the page table is obtained. The .beta.-th record's content PFRA counting from the head address of the page table is obtained by using the page number .beta., thereby forming an upper part of the real address. The byte displacement .gamma. of the virtual address is added as the lower part of the real address, thereby forming the real address. Regardless of whether the logical page is divided into the segment number and page number, it will increase the time necessary for the address translation to provide the page table in the main storage. In order to speed up the address translation, translation lookaside buffer (TLB) is provided as shown in FIG. 3. The translation lookaside buffer (TLB) is composed of an associative storage hardware having several tens to 256 entries. The translation lookaside buffer has a set comprising a valid bit, a logic page number (comprising a segment number and page number) a physical page number and segment table designation STD. The number of the set corresponds to the number of entries. For every memory access, a segment table designation STD of an address space to be accessed is compared with the segment table designation STD of the TLB and if a corresponding STD exists, the TLB is used. The comparison can be simultaneously performed for all the entries at high speed. If the STD of the address space to be accessed does not correspond with the STD in the TLB, the physical page number is determined by the above recited DAT.
The translation lookaside buffer is considered as a kind of associative mapping and comprises a table of the addresses which are most likely to be used and which are selected from all the addresses. This is effective because of the principle of localism.
The paging does not require an addition for the address translation. The address translation can be performed at high speed by using the translation lookaside table. The memory management is also easy because all the pages stored in the main storage are unlikely to be used again in the near future and the effectiveness in utilizing the main storage is high.
As shown in FIG. 2, when the number of multiple levels is two, the head address of the segment table can be obtained by using the segment table designation of a control register. As shown in FIG. 2, the structure for realizing a virtual storage with more than three levels is an extended space addressing structure. The extended space addressing structure translates an operand address of the instruction to a dynamic address by using an access register and an access list provided in the main storage. When dynamic address translation is performed, the data space segment table corresponding to the respective data space and the page table corresponding to the address space are used.
The lower portion (16 bits) of the access register with a width of 32 bits, for example, has an entry number ALET(0-65536) of the access list. Respective entries in the access list have widths of 16 bytes, for example. The field of the width of 25 bits of the access list has an ASN second table entry with a width of 24 bytes and a segment table destination STD with a width of 32 bits for the data space provided therein. This pointer mechanism indirectly performs an addressing of the data space by using 16 bits (ALET) in the access register, that is, the 16 bits (ALET) are added to the 31 bits addressing for the space address, thereby providing an architecture for 47-bit addressing. This technology is recited in detail for a Nikkei computer Sep. 12, 1988, pages 105 to 109.
In this multi-virtual storage system, a plurality of tables, namely, an access register, an access list and an ASN second table are sequentially accessed and the segment table designation can thereby be obtained. Therefore, there is a problem that it takes time to obtain the segment table designation. In the conventional art, to solve this program, an access register translation lookaside buffer (ALB) must be able to carry out a translation from the content (ALET) of the access register to the segment table designation at high speed, thereby obtaining a segment table designation at high speed.
First, one of the access registers is selected by the base register number, ALET is read out and then the access register translation lookaside buffer (ALB) is accessed by this read out ALET. When the valid entry having ALET which accords with the ALET read out from the access register exists in the ALB, the segment table designation stored in the entry is determined as the segment table designation for the main storage access. The determined segment table designation is thereby transferred to the dynamic address translation structure. When there is no valid entry in the access register translation lookaside buffer (ALB), the access list and ASN second table is sequentially accessed to provide the segment table designation. This segment table designation is determined as the segment table designation for the main storage access and is transferred to the dynamic address translation structure. Separately from this operation, in the conventional art, two address spaces comprising a primary space and a secondary space are designated by segment table designations in two control registers.
However, in such prior art technology, ALET is read out first and then the access register translation lookaside buffer determines the segment table designation in accordance with ALET, thereby providing two operation steps. Therefore, it takes too much time to obtain the required segment table designation. The problem is made more serious by the delay of the hardware, which occurs because the hardware of the access register and the access register translation lookaside buffer cannot be provided in the main part of the CPU. Namely, the volume (4 bytes.times.16) of the access register becomes relatively large. The volume of the hardware of the access register translation lookaside buffer becomes large so that the access register can have many effective entries. Therefore, this hardware can not be provided in the main part of the CPU, thereby causing the delay to be greater. Thus, the prior art has the problem that a high speed data process cannot be carried out.